The present invention relates to integrated circuit structures and their fabrication, specifically to bipolar transistors.
Bipolar junction transistors (BJTs) are frequently used in integrated circuits, and are often fabricated within the process flow for field effect transistors, such as in a standard CMOS process. The emitter efficiency in a bipolar, which determines the gain of the device, depends heavily on the emitter doping, which in turn depends on the implants used in their formation. Often, implants that exist in the standard CMOS are modified, or new implants are added, in order to create bipolar devices using existing device features. One possibility is to use the source/drain areas of existing devices to form the BJT, or part thereof.
In advanced CMOS process, the source/drain junction becomes very shallow to support a short channel length. In such shallow diffusions, the minority carrier diffusion length in the shallow source/drain junction is determined by the junction depth rather than doping density in the emitter. Thus, efficiency improves when the junction becomes deeper.
In some conventional designs, for example, a vertical pnp BJT is formed by using the p+ source/drain implant to form the emitter, and using p-well and n-well implants to form base and collector. However, the gain of such a BJT is typically only about five, which indicates a very low emitter efficiency.
Vertical PNP Bipolar Device With High Emitter Efficiency
The present application discloses an improvement to the performance of a vertical bipolar transistor which can be obtained using a typical CMOS process without additional mask steps. In the preferred embodiment, the emitter efficiency of a vertical pnp bipolar junction transistor is improved by reducing the depth of the p well implant, increasing dopant concentration in the emitter region and also decreasing the dopant concentration in the base. A high energy blanket boron implant is used in some embodiments for n well to n well isolation.
Advantages of the disclosed methods and structures, in various embodiments, can include one or more of the following:
higher emitter efficiency;
fully compatible with standard CMOS process;
forms a BJT with no added mask steps.